1. Field of the Invention
The present invention relates to a demultiplexer system used in digital communication and particularly to frame synchronizing suitable for use in a byte multiplexing system.
Digital communication systems employ byte multiplexing transmission to increase the transmission rate on a transmission path, and thus to improve communication efficiency.
FIG. 1 illustrates the multiplexing/demultiplexing of a plurality of channels in a known byte multiplex transmission system. In FIG. 1, a plurality of 8 bit frame bytes F1 are input via channels C1-C4 to a multiplexer 10 at a basic speed. The frame bytes are multiplexed by multiplexer 10 and transmitted as byte multiplexed data 5 at, for example, four times the basic speed. The frame bytes Fl corresponding to channels C1-C4 (called a frame) are received by a demultiplexer 20.
In a byte multiplexing transmission system such as shown in FIG. 1, it is desirable to simplify the detection and synchronization of a frame pattern of a frame to ensure effective and efficient demultiplexing.
2. Description of the Related Art
FIG. 2 illustrates data in a transmission format as transmitted over a transmission line. In the FIG. 2 format a frame comprises four data bytes. FIG. 2 illustrates two frames, the first comprising bytes F1 and the second comprising bytes F2. Reference characters C1-C4 indicate channels C1-C4; ID denotes identification bytes for identifying the channel numbers and D denotes data bytes, each data byte comprising 8 bits. For transmission systems utilizing this data transmission format at least two methods of frame pattern detection and demultiplexing are known.
Referring to FIG. 3A, frame pattern detection is carried out periodically. A frame pattern comprising frames F1 and F2 is detected. The detection is executed once every fourth byte at the time indicated by the arrows, which correspond to channel C1. The detection of every fourth byte establishes a reference byte which is used to establish frame synchronization. Thereafter, the channel number is identified by the identification byte ID and the bytes are matched up with their respective channels and returned to the same sequence as they existed prior to multiplexing.
In the frame pattern illustrated in FIG. 3A, only the bytes of channel C1 need be detected to establish frame synchronization. Therefore, the circuit required for frame pattern detection using the frame pattern of FIG. 3A does not need to be very complex. However, the channel number sequence for the multiplexer must be identified with the identification byte ID so that the demultiplexer can output the data in the proper sequence. This requires additional hardware which complicates the circuit. The demultiplexing process is delayed because the bytes cannot be redistributed to the proper channels until the ID byte is detected and used to correlate a frame byte with its proper channel.
Referring to FIG. 3B, all frame bytes are detected simultaneously. Frame synchronization and identification of channel numbers are accomplished simultaneously by detecting, at one time, all bytes of frames F1 and F2 of channels C1-C4 from the transmission format illustrated in FIG. 2.
In the frame pattern illustrated in FIG. 3B, all of the multiplexed frame patterns must be detected. Accordingly, the identification byte ID is not needed. However, because all of the bytes must be checked during the pattern detection process (for example detection must be done for total of 64 bits (8 bits.times.8 bytes)), the circuit for the detection circuit is very complicated and the speed is diminished because of the time required to detect all of the bits.